The present invention relates generally to the field of digital data communications. In particular, the present invention relates to data link controllers (DLC) capable of receiving data in a serial format and performing a serial to parallel conversion on the received data.
Some data communication protocols, for example X.25, contain characters ranging from five to eight bits in length. These characters are typically received by devices which operate on bytes of data. As the characters contain fewer bits than required for a full byte, additional bits must be added to the character bits to form a full byte corresponding to each character. The data communication protocols permit the characters to be stripped of these superflous bits and concatenated into an information field (I field) of a packed bit stream for transmission, in order to utilize the full bandwith of a given communications network. Generally, the DLC receiver will receive and store the I field in eight bit byte segments, which can result in the last segment being incomplete if the length of the received characters is less than eight bits or one byte. In other words, the I field is segmented into eight bit bytes and the bits left over after segmentation consitute bit residue. For example, if the character length is five bits and five characters are received, the DLC will break the twenty-five total received bits into three eight bit byte segments with a single bit remaining in the last segment.
The DLC receives each character of the I field in a reciver buffer having a plurality of shift registers that receive data serially and transfer the data out in parallel to a memory device such as a first-in first-out (FIFO) buffer. If the communication protocol transmits defines the first bit of a character to be transmitted as the least significant bit (LSB) of a character, then the shift registers serially receive data into what can be defined as the shift registers most significant bit (MSB) position first and the data is serially shifted within the registers every time a clock signal is received until the shift registers are filled with a full byte of data. A parallel transfer operation is then performed by the last shift register to transfer the data byte contained in the last shift register into the FIFO. The data bytes stored in the FIFO may therefore contain data bits from more than one character if the character length is less than the number of bits in a byte.
The above-described operation of the shift registers, however, creates a problem with respect to the bit residue as a full byte of data is not serially loaded into the shift register prior to the parallel transfer operation. For example, if the bit residue constitutes five bits, the three least significant bits of the last shift register will not be filled. Thus, some mechanism must be provided to fully shift the five residue bits in the last shift register until the least significant bit (LSB) of the shift register is filled, while at the same time filling the three most significant bits of the register.